R0K561668S000BE【PDF 15/50 页】KIT STARTER FOR H8SX/1668

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13

On-chip Peripheral s : Computer I/F

■ Low-Pin-Count (LPC) Interface

LPC

PCI/Ho s t Bu s

? A popular interface to communicate

to P C chip set used in notebooks

and P C servers

? P erforms serial data and address

transfer usin g 33MHz clock

Diagram

Ho s t

LPC

? Supports I/O read and write cycles

Fla s h

Super I/O

Embedded

? Supports serial interrupt

on sin g le line

? Supports power-down mode

BIOS

KBC

PP

SP

FDC

Controller

? Reduced pin count

H8S/21xx

■ Keyboard Buffer Controller (KBC)

? Conforms to P S/2 specification

KBC

Diagram

Keyboard

n

? Error detection, parity error and

stop bit monitorin g

0

1

2

3

. .

.

? Five host interrupt requests

Inputs

Scan

Matrix

H8S

Output

■ On-chip Bu s Controller (B S C)

? P rovides g lueless interface with external devices

? Supports basic SRAM, burst-ROM interface

. .

.

? Mana g es external, addressable

16MB re g ion (8 different areas)

? Bus specification can be set

BSC Diagram

independently for each re g ion

? Selectable 8- or 16-bit bus width

? Choice of 0 to 7 pro g rammable

External bu s control s ignal s

Bus

controller

Internal control s ignal s

Bu s mode s ignal

wait-state access

BCR

? Supports direct connection to

S D RAM on selected devices

WSCR

? Includes a bus arbiter for

bus mastership arbitration

? Burst ROM interface

can be set for area 0

WAIT

Wait

controller

CPU bu s reque s t s ignal

DTC bu s reque s t s ignal

? External write cycle and internal

access can be executed in parallel

? Idle-cycle insertion capability

Bus arbiter

CPU bus acknowledge signal

DTC bu s acknowledge s ignal

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